Modern integrated circuits are formed on semiconductor chips. To increase manufacturing throughput and lower manufacturing costs, the integrated circuits are manufactured in semiconductor wafers, each containing many identical semiconductor chips. After the integrated circuits are manufactured, semiconductor chips are sawed from the wafers and packaged before they can be used.
In typical packaging processes, semiconductor chips (also referred to as dies in the art) are first attached to package substrates. This includes physically securing the semiconductor chips on the package substrates and connecting bonding pads on the semiconductor chips to bonding pads on the package substrates. Underfill, which typically comprises epoxy, is used to further secure the bonding. The semiconductor chips may be bonded using either flip-chip bonding or wire bonding. The resulting packages are referred to as ball grid array (BGA) modules. A plurality of chips having different functions may be integrated in a same BGA module to form a system-in-package (SIP) module.
FIGS. 1 and 2 illustrate cross-sectional views of intermediate stages in the packaging of semiconductor chip 100 onto package substrate 110. Semiconductor chip 100 includes bumps 102 and flux 104 on bumps 102. Package substrate 110 includes solder bumps 112. The positions and pitches of bumps 102 and solder bumps 112 are designed to accurately align to each other. However, since package substrate 110 (and/or semiconductor chip 100) has multiple layers formed of different materials, solder bumps 112 may have position shift (as symbolized by arrows 114) caused by the stresses resulted from the multiple layers. The position shift may cause the pitches between solder bumps 112 to be changed from the designed values. As a result, as shown in FIG. 2, when semiconductor chip 100 and package substrate 110 are bonded together, bumps 102 and solder bumps 112 are no longer accurately aligned. This may cause further stress to semiconductor chip 100 and may cause an open circuit in the case, if some of bumps 102 are fully misaligned to the corresponding solder bumps 112.